Thu Jul 17, 2014 12:22 am
If you think about the fact that most RISC processors are similar evolved at the time, the number of instructions per clock cycle is somehow on par.
(They would not be able to sell a less powerful processor with almost the same price, since that price is almost linear with the chip surface).
So really, I would not expect some spectacular differences between the two architectures.
Usually, on embedded devices, the co-embedded peripherals make the difference, in this case e.g. hardware encryption support.
Also the speed of RAM is a big showstopper (not the case @500MHz) because it limits the amount of data that can be manipulated per time unit.
So IMHO on single thread code they should be on par.
But think of the fact that the 850 will be dual core. So even if there is a single thread for an action, it can have the whole core to itself while householding OS tasks can be offloaded to the other core, which is not possible for a single core device.
Compared to the current devices, the 850 will probably be able to achieve 50% of the RB1100AHx2 performance (which is PPC clocked at 1066MHz). And this is almost double in regard to the 2011 performances.
It is also interesting to know if the 850 will have a switch chip or direct connected ports, since the PPC allows for 5 Gb ports, which will increase the potential throughput in routing applications by eliminating the bottleneck between the CPU and the switch chip, but at the same time limiting the throughput if switching is needed (probably there's no win/win here, unless there is switching support in the chip or fastpath can do miracles on a bridge).