Does HAP-AX3 and HAP-AX2 support hardware accelerated switching with VLANs?

I can see on the block diagram that the IPQ6010 SoC is responsible for everything, including swtiching:

https://i.mt.lv/cdn/product_files/C53UiG5HPaxD2HPaxD_221052.png

Can I add two separate bridges with VLANs and use hw accelerated switching on them? Or does it work only when a single bridge is used?

Thank you,

Laszlo

Limit of one bridge per switch chip (able to be offloaded) is present since forever and I didn’t see any changelog entry which would announce a change.

Is it any different for 98DX3216 or 98DX3236 (CSS326 and CRS326)?

No, it seems it’s a limitation of how ROS offloads bridge to HW.

OTOH there are only a handful reasons to use more than one bridge (where appropriately configured single bridge simply wouldn’t do) … so it might be you don’t actually need multiple bridges.

And any switch running SwOS (e.g. all CSS devices) work as if it was running single bridge.