I realize the ether ports on the 493G are split between two switch chips. I’m wondering if there is any specific information on how the system will behave if I bridge the interfaces between the switch chips. Right now, I have ether 2,3,4,5 bridged and have a DHCP server set up on the bridge. I have two questions:
I assume that traffic coming in on one of those ports and bound for a host on another of that switch’s ports doesn’t go all the way up to the bridge, it just goes through the switch and out the correct port, and won’t impact the system CPU performance, is this correct?
If I were to add the ports on the other switch chip (6,7,8,9) to that bridge, will that impact performance between hosts only on one or the other switch? I guess I’m asking if only time packets will get passed up the the bridge (and therefore, the system CPU) is if they don’t match any physical addresses already on that particular switch, and need to get either routed out of the network (onto the internet in my case) or onto the other switch?
I assume that traffic coming in on one of those ports and bound for a host on another of that switch’s ports doesn’t go all the way up to the bridge, it just goes through the switch and out the correct port, and won’t impact the system CPU performance, is this correct?
If I were to add the ports on the other switch chip (6,7,8,9) to that bridge, will that impact performance between hosts only on one or the other switch?
Performance of all host may be affected as the bridge will utilize CPU resource.
The other switch chip includes interfaces 1,6,7,8,9, and I’m using ether1 as my outside, public WAN interface, so if I create a master port on that switch, I’ll be including that public interface in the switch as well, correct? Is there any way around that, i.e. to be able to switch ports 6,7,8,9 but not include 1?