I don’t think either the hap ax2 or hap ax3 switch chips are currently supported for HW vlan-filtering, so the bridge vlan-filtering is already done in the CPU, although I am surprised that the behavior would be different in the software implementation (other than the L2 forwarding performance and CPU loading).
If you want the CPU to be able to “connect” to the vlan in the switch ASIC, that’s the purpose of including the bridge in the /interface bridge vlan for each vlan you want the CPU to see. When HW offloading to switch, the CPU won’t ever even see the traffic that stays within one vlan between two switch ports, but the only way for traffic to get from one vlan to another is via routing, usually by the CPU on low end switch chips, and that requires the “connection” from the vlans involved to the CPU via the “internal trunk link”. See @sindy’s RouterOS bridge mysteries explained (and this post and the one following it discuss my interpretation about it a bit more).
If you want to discuss this more, we should create a new topic instead of hijacking this one, more than we already have.