I see the CRS326-24G-2S+ has a block diagram but not sure if the internals are the same.



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So... I'm going to assume that, at the very least, the way the switch controllers are configured are the same as the CRS.

A controller for each group of 8 gigabit ports and one for the 10gig ports.

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I think you misread those diagrams.
It is not a controller for each port group. It is a octal PHY (physical interface transceivers to MII converters, 8x1Gb eth to 2x4Gb MII in this case) for each group, and it has no user relevance unless one gets blown out and knocks out the whole group.
The controller is still a single one, containing the 26 port switch chip to which the 8 resulting MII interfaces are connected (6x4Gb and 2x10Gb).

I think you misread those diagrams.
It is not a controller for each port group. It is a octal PHY (physical interface transceivers to MII converters, 8x1Gb eth to 2x4Gb MII in this case) for each group, and it has no user relevance unless one gets blown out and knocks out the whole group.
The controller is still a single one, containing the 26 port switch chip to which the 8 resulting MII interfaces are connected (6x4Gb and 2x10Gb).

Ok... I guess I did misread them? I don't know. So you're saying I don't need to group all of one type of device traffic together in one 8 port group for maximum throughput efficiency?

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Exactly. Only the media interfaces are grouped by the fact that they use octal interface chips. The actual switching is done in the central switch chip and the hole thing works at wirespeed and there is no data shortcut inside those PHYs. Everything still flows through the MII buses to the switch chip and back.