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CCR: how many macaddress?

Mon Nov 19, 2012 4:11 pm

Hi :)

Two quick questions regarding the cloud router:
  • how many macaddress can be stored in the forwarding table? Is this per-unit or per-bridge? (i.e., in the RB1100AHx2, I see that the Atheros chipset has a limitation of 2k MAC per-chip)
  • is there any support for PVST+?
Thanks!
 
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tomaskir
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Re: CCR: how many macaddress?

Mon Nov 19, 2012 4:29 pm

PVST(+) is cisco propietary. MSTP is not supported.

RSTP and STP are fully supported.
 
Neilson
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Re: CCR: how many macaddress?

Tue Nov 20, 2012 5:45 am

More experienced people can probably answer this / correct me

As I understand it that 2K limit is simply the mac address limit on the switch chip in the 1100AHx2. The box itself for routing etc isn't limited the same way.

The CCR series do not use switch chips, all ports are connected directly to the CPU and all the processing is done in that core. Therefore no switch chip to have this limit, it simply becomes a limit of any programming or storage limits imposed by the system or software.

I would hazard a guess that no practical limit exists.

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Alexander
 
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janisk
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Re: CCR: how many macaddress?

Wed Nov 21, 2012 3:40 pm

when we talk about software feature most often limit is the amount of available RAM. Since CCR has 64bit address space you can have 16GB of ram and that is a lot.
 
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Re: CCR: how many macaddress?

Wed Nov 21, 2012 4:26 pm

PVST(+) is cisco propietary.
True but not completely relevant, both Juniper and Huawei implement a PVST-compliant algorithm on their switches.
 
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Re: CCR: how many macaddress?

Wed Nov 21, 2012 4:27 pm

As I understand it that 2K limit is simply the mac address limit on the switch chip in the 1100AHx2. The box itself for routing etc isn't limited the same way.
I'm talking about forwarding, not routing.
The CCR series do not use switch chips, all ports are connected directly to the CPU and all the processing is done in that core. Therefore no switch chip to have this limit, it simply becomes a limit of any programming or storage limits imposed by the system or software.
So, all switching is done in-CPU? On a general-purpose core (like the Tilera one) that would be far from "wire-speed"!

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