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ttys0
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Should hardware offloading be enabled on both switch cpus?

Mon Jun 27, 2022 11:50 pm

I have a CRS-354 switch, and am curious about whether l3-hw-offloading should be enabled on both the Marvell and the Atheros chips. Documentation tends to only refer to set 0 which refers in this case to switch 1, or the Marvell chip. It's unclear to me what the second chip is for, and if l3-hw-offloading should be enabled on it as well.

# NAME     TYPE              L3-HW-OFFLOADING
0 switch1  Marvell-98DX3257  yes
1 switch2  Atheros-8227      no
 
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Re: Should hardware offloading be enabled on both switch cpus?

Tue Jun 28, 2022 1:30 am

in ports you can see which ports belong to which chip

i think atheros is for MGMT interface only, please do not bridge your management interface with hardware offload ones
 
ttys0
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Re: Should hardware offloading be enabled on both switch cpus?

Tue Jun 28, 2022 1:44 am

Ahhhh, didn't even think to look there. Yeah, all my LAN ports that I have in a single bridge, and my WAN port, are on switch 1. The management port is on switch 2.

Thanks so much. I was hoping that I was just missing something obvious, and it turns out I was. :)

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