RB3011 Block diagram?

When it would be possible to buy 3011?

HW crypto! That makes me :smiley: :smiley: :smiley:

excellent news.
even 20% stock overclocking :wink:
1-1.2GHz. if ROS allow and RB3011 had SOLID/Huge heatsink on CPU/SoC - it mayb had even bigger space for over-clocking, especially for consumers, improving/replacing heatsink with something more serious/expensive.
AES offloading, IPSec and routing. also chips had PCIe, SATA port, audio interface(mind VoIP boxes build over it :wink: and xGMII allow you to use state-of-the art PHy’s use(especially nice made by Atheros and big Qualcomm too).
memory controller support only low-clock 1033 DDR3, but works fast by itself(no mult-channel IMC or HBM in low-end CPU’s)
serial port mean potentiall console port too, along with USB3, in rb450g/rb850gx2 -style in next variations of RB3011(which isn’t critical for me, but still used by some).

note: its nearly 4x faster than best MIPS32 and about 2.5x-3x faster than any kind of MIPS64 chips(including Cavium, Tilera and etc) on same clock and fast/big caches mean less waiting for memory controller.
“2x rb2011 performance” imply that “offloading” marketing ploy isn’t used, which is COOL, cuz most implementations was buggy as hell(Qualcomm-made - probably least buggy, IMO) and imply using some kernel hacks/tricks and result with both security issues and netflow delays.

so bottom line: its Perfect choice for SOHO devices.
backed with decent RAM amounts it can do really Adequate (to present ISP subscriptions rates/bw), which previous entry-level RB devices fail, sadly.
very curious about possible SD clot presence or possible eSATA port on devices(even w/o DLNA support/package, sFTP/SMB resources wasn’t uncommon among RB users, despite extremely slow performance).
those chips didn’t support dedicated bus for multi-CPU devices and never intended for such, but PCIe interfaces may be used for such.
as you can see from aged aricles
http://www.anandtech.com/show/6568/qualcomm-krait-400-krait-300-snapdragon-800
http://dishank1.blogspot.ru/
http://en.wikipedia.org/wiki/Krait_(CPU)
Krait 300 core aren’t as cool as A15/A17 cores or other ARMv7 things, but really impressive.
newer IPQ, based on ARMv8, whose eventually come to IPC8064/IPQ8064 replacement (and/or four and quad -core versions of it, probably) - may be lot MORE faster (https://www.qualcomm.com/media/documents/files/snapdragon-801-processor-product-brief.pdf ), but even Krait 300 cores in IPQ8062 processor - can be VERY fast(in SOHO/home terms/scale). 1M L2 cache(512Kb per/core) also helps much(but L1 remain relatively small 16/16kb) and vFPU and NEON usage can speed-up math/computation DRAMATICALLY.
not sure about SMT support in Krait 300 cores.

p.s. still unclear/unlikely was StreamBoost/adaptive QoS support in ROS aswell as support for AllJoyn mesh/ad-hoc networking.
there was also indirect suggestion about SMT(2x threads per core) in Krait 300 cores
http://events.linuxfoundation.org/sites/events/files/slides/ELC2015v2.pdf
http://pages.cs.wisc.edu/~danav/pubs/qcom/hexagon_hotchips2013.pdf
also new/updated Qualcomm radios, possibly used in RB3011 provide smooth pathway for MU-MIMO adoption by RB devices
http://www.qca.qualcomm.com/wp-content/uploads/2015/01/802.11ac_MU-MIMO_Bridging_the_MIMO_Gap_in_Wi-Fi.pdf
http://www.qca.qualcomm.com/thewire/mu-mimo-ecosystem-mu-efx/
https://www.qca.qualcomm.com/products/qualcomm-vive/
(there was number of radios for each band, released by Qualcomm), aswell as 801.11ac v2.0 and 802.11ad 802.11ax adoption(however 60GHz radios slightly lag to market).

So both the Tilera and the IPQ are network processors? I.E. CPU’s with a special purpose.

Does anyone know how their achitecture differs? I can’t really find a definitive source on the Tile achitecture.

My guess was within the ballpark, then. :wink:

– Nathan

Wait…say what? Pretty sure Tile architecture is not related to MIPS64. But if I’m wrong, [citation needed]. :wink:

– Nathan

in fact they are.
http://en.wikipedia.org/wiki/TILE64
“… MIPS-derived VLIW instruction set…”
its was started as exascale-goal DARPA project 18 years ago ago(while even Twin-core CPU’s wasn’t uncommon, yet, even in enterprise market) with emphasis on dense multi-core design low-slilicon-usage, high-bandwith, low-latency interconnect/fabric, connecting chip together,(chips with more than 128 cores(goal was up to 1024 and beyond)probably get internal optical bus.
http://en.wikipedia.org/wiki/Tilera
its heavily used/advertised in IPS/networking, but major targeted sector was HPC, military and aerospace, but due to bigger clocks, latency(and size/delay of caches, IMC imprtfactions and etc) issues become less problem, than suggested initially.

its seriously customised during design, and differ from genuine MIPS64, yes(thats reflect includsion as separate Architecture into linux kernel/toolchain 5yrs ago), but so did Cavium with MIPS64 during design, Lexra and other ARM/MIPS/PPC suppliers.

Tilera presently aquired by EZ Chip(networking/military semiconductor company from Israel)10 months ago.
http://en.wikipedia.org/wiki/EZchip_Semiconductor

p.p.s.
VLIW-emphasis in design, imply very Dramatical dependency on compiler profiling/optimisation in achieving DECENT performance, but overall bang/clock/silicon may be notably bigger, like in IA64, R500 and FR-v arch, before(some may remember former VLIW5 GPU chips from AMD :wink:, while many-core design by itself - imply HUGE processing power(and power consumption :wink:
presenly ROS didn’t support VLIW features/offliading in Tile chips so talking about Tile64-sepcific differences from MIPS64 wasn’t make much sense, yet.
same about Zero-overhead linux -alike build/approach to networking firmware engineering/architecture, not adopted by MikroTik, yet, sadly, but promising VERY dramatically improve latency/response and even better do with scalability(per/cores).
personally i think for both SOHO and SMB - Tile64 was overkill(too expensive, too hot, not so available), while Krait 300/400 and newever IPQ(probably ARMv8-based) probably fits better.
im may be wrong with something/anything i wrote above, but AFIK its looks like that.

you can get datasheets(brief for free and complte as part of SDK and evalution boards)for their chips , but Tilera didn’t ecourage sharing whitepapers with outsiders by anyone under NDA or other agreements.
http://en.wikipedia.org/wiki/TILE64
http://arstechnica.com/gadgets/2007/08/mit-startup-raises-multicore-bar-with-new-64-core-cpu/
http://arstechnica.com/gadgets/2007/08/mit-startup-raises-multicore-bar-with-new-64-core-cpu/2/
and since EZ aqusition - majority of datasheets was removed from public.

major, distinct Tile64 feature - wasn’t VLIW offliading or ultra-dense many-core design, but Very efficient internal mesh interconnect within chips.
they are remain VERY expensive, sadly(up to hugreds times more than IPQ chips for some bigger models), for mass-market.

Wow, you could have an optical audio port, like an Airport Express, straight from the chip.

(but AE also does analog from the same port)

well, more usually such devices(not routers, but usually ordered by their ODM, by huge ISP, directly, all-in-one internet&tv&phone&security devices)use simply analog audio input/outputs, ie copper-based. also AFIK, both Apple, Samsung, Google and Microsoft shifts toward DLNA and bluetooth sound support, rather than hardwired audious(in both ways).
does “Airport” had eSATA ports ? or had PCIe interfaces ? how many Airport devices had(full-scale A-type !!)USB3.0 port ?
generally “Airport” is just a brand. and include historically many devices, including 24k arch chips, ubicom devices and even lexra SoC once(if im not mistke that with something) and many other options under hood.

When will it be available RB3011 about? Alternatively, the processor will I give to CRS?
thanks

Anything on the physical dimensions?

I think - the same as rb2011

I heard that, but the RB2011 sheets just list the PCB dimensions, not the case dimensions.

rb2011 - Dimensions 230x90x25mm, Weight (board with LCD): 233g

judging from picture and anounced intent/placement as drop-in replacement/upgrade for rb2011 - it may be identical to rb2011, except differences in USB port size/place and power jack location.
which make lot sense both for end users and telecom market and help model adoption in last case especially.
similarly we may expect ultra-compact version on same chip to replace 951 models.
and after they released, there may be rb4011 on quad-core equivalent with a53-based crait cores and 14nm silicon(but even 28nm would b LOT colder/faster than previous mips chips)
perordered some to play with.

Where did you pre-order?


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I hope this device will have a Hard Disk Connection.
That we finally can add a SSD HD.

What are you going to do with a SSD inside low power router?

Store porn for faster hand job :laughing: